1. Field of the Invention
Embodiments of the present invention relate to a test pattern for analyzing capacitances of interconnection lines in a semiconductor device.
2. Discussion of the Related Art
In general, a comb-type capacitor or a plate-type capacitor has been used as a test pattern for measuring and analyzing capacitances of interconnection lines to exhibit characteristics of the interconnection lines in a semiconductor device.
In the test pattern, pads for probing are connected to capacitor Devices Under Test (DUTs) through the interconnection lines. However, a capacitance value, as measured by probes connected to the pads, is higher than the actual capacitance value of interest.
The reason for this measurement discrepancy is that parasitic capacitance components attributable to the pads and portions of the interconnection lines leading from the pads induce inexact capacitance values in the measurement and analysis of capacitances of the interconnection lines.
Thus, a method for measuring and analyzing capacitances of interconnection lines using a null pad pattern, which is separately provided to determine parasitic capacitance components, is conventionally applied.
Hereinafter, a general test pattern for analyzing capacitances of interconnection lines and accounting for parasitic capacitance components using a null pad pattern will be described with reference to FIGS. 1 and 2.
FIG. 1 is a view illustrating the test pattern for analyzing capacitances of interconnection lines and accounting for parasitic capacitance components using a null pad pattern.
As shown in FIG. 1, the conventional test pattern for analyzing capacitances of interconnection lines in a way that accounts for parasitic capacitance components includes a comb-type capacitor module (Ma), and a null pad module (Mb) for determining parasitic capacitance components.
The comb-type capacitor module (Ma) includes a first metal line 2a having a comb-type structure including a plurality of tines and a second metal line 2b having a comb-type structure including a plurality of tines engaged with (i.e., formed between alternate ones of) the tines of the first metal line 2a. The comb-type capacitor module (Ma) also includes a first probe pad 3a connected to an end terminal of the first metal line 2a, and a second probe pad 3b connected to an end terminal of the second metal line 2b. 
The null pad module (Mb) includes third and fourth metal lines 2c and 2d, each of which has a linear structure, and third and fourth probe pads 3c and 3d, respectively connected to end terminals of the third and fourth metal lines 2c and 2d. 
Now, the above test pattern will be described in detail with reference to a circuit diagram and algebraic expressions below.
FIG. 2 is a circuit diagram representative of FIG. 1.
In the comb-type capacitor module (Ma) and the null pad module (Mb) of FIG. 2, Cp represents a parasitic capacitance component due to the pads and lines 2c and 2d leading from the pads, and Ci represents a capacitance of a main interconnection line, which is of interest for modeling, i.e., the capacitance of a main capacitor DUT corresponding to the tines of the comb-structures, as shown in FIG. 1. The relation between these numerical values is obtained by the following algebraic expressions.Cta=Cp+Ci Ctb=CpCi=Cta−Ctb 
Here, Cta represents the total capacitance measured by the comb-type capacitor module (Ma), and Ctb represents the total capacitance measured by the null pad module (Mb).
Parasitic capacitance can be measured by the above-described method. However, the null pad module, which is additionally provided to determine the capacitance Ci required to exhibit characteristics of the interconnection lines in the semiconductor device, occupies valuable space in the semiconductor device.